Who Captures the AI-Test Dollar in Southeast Asia?
A valuation map of the listed semiconductor-test and OSAT names, from Bursa and SGX (KESM, AEM) to Taiwan- and US-listed peers like KYEC (2449), ASE (NYSE: ASX) and Trio-Tech (TRT).
AI accelerators are making semiconductor test more valuable, more geopolitical, and more Southeast Asian. The question is which listed names actually capture the economics, and which already price it in.
The most expensive silicon in the world does not ship when it leaves the fab. It ships when someone proves it works.
For AI accelerators, that proof is getting harder, longer and more valuable [2]. A modern accelerator has to be probed, packaged, burned in, and increasingly run through a full system-level rehearsal before it goes anywhere near a data centre. The result is that test is moving from a back-end afterthought to a front-line bottleneck, and as customers diversify their back-end supply chains away from Greater China, more of that bottleneck is being relieved in Southeast Asia.
That sets up a simple investment question: who actually captures the AI-test dollar, the independent tester, the turnkey OSAT, the equipment supplier, or the customer that owns the tools? The answer is not “every OSAT.” Pure-play testers, integrated packaging houses and equipment suppliers sit in different layers of the stack, run on different qualification clocks, and trade at very different valuations. Some independent testers still trade like cyclical back-end shops; some AI-adjacent names already trade at equipment-like multiples.
Our thesis, in three lines.
AI accelerators are raising the value of semiconductor test, but the economics do not accrue evenly.
The best near-term exposure is not the largest OSAT; it is the already-qualified independent tester or the equipment supplier that catches the first wave.
The main risk is the 2027 capacity wall, the point where today's qualified scarcity meets new integrated capacity: once it arrives, the highest-volume AI work can migrate into captive or integrated lines, so valuation, not headline exposure, is the whole game.
This is not a screen of Southeast Asia-listed companies only. It is a map of who captures the test economics of Southeast Asian back-end migration: local listed names across independent test, OSAT and equipment (KESM, Inari, Unisem, MPI, AEM), foreign names building regional capacity (KYEC, ASE, Chipbond, Trio-Tech), and the equipment leaders and specialists whose tools set the margin pool (Advantest, Teradyne, Aehr). We map who does what, who catches the first wave, and, for paying subscribers, where the valuation gap looks most interesting.
What semiconductor test is, in plain English
Think of the back end as four gates. Probe the die while it is still on the wafer, package it, test the finished package, then stress it under real-world conditions. AI makes those gates more valuable because the parts passing through them are worth thousands of dollars each, and because a modern accelerator is not one chip but a stack of chiplets and high-bandwidth memory (HBM) bonded onto an interposer, the small slab that wires them together. Once those pieces are bonded, rework is essentially impossible, so every die has to be proven good first. Some industry estimates put test at roughly 5% to 10% of the cost of a leading-edge AI part, up from low-single digits for a conventional chip [6][7]. Test has moved from the end of the line toward the front of it.
Two distinctions run through the whole piece. First, whoever owns the tester matters: the core testers, the automated test equipment (ATE), are dominated by Japan's Advantest and America's Teradyne, on the order of 80% of the high-end tester market between them, though share estimates vary by how the market is defined [1][3], and a test house either owns its machines or runs them on consignment for a customer, which changes the margin. Second, an independent test house (also called a merchant tester) sells test as a service and is not owned by or affiliated with a chip customer, while an integrated OSAT folds it into packaging. Those two compete for the same AI work by different routes.
It helps to see the whole thing as a stack, because the Southeast Asian listed opportunity is not spread evenly across it. It is thin in the tester layer, which is a foreign duopoly, and thickest in the test-service layer and in the handler and system-level-test niche where Singapore's AEM sits.
One honest caveat frames everything. The most leading-edge packaging, the CoWoS-class interposers (TSMC’s advanced chip-on-wafer-on-substrate method) and the HBM stacking closest to the AI die, largely stays captive inside the foundries and IDMs (TSMC, Intel, Samsung, SK hynix), because it is too tightly coupled to the front end to hand off [11][35]. What actually outsources to independent houses in Southeast Asia is chiefly final test, burn-in and mid-tier packaging. Even at the leading edge, testing is the minority of the dollar: ASE puts its own advanced packaging-and-test revenue at roughly 75% packaging and 25% testing [24]. That is why test, not packaging, is the right lens here.
The money is following the difficulty. SEMI expects semiconductor test-equipment sales to rise about 48% to roughly US$11.2 billion in 2025 [8]; the broader outsourced assembly-and-test market is put near US$47 billion now, heading toward US$71 billion by 2030 [9]; and the slice that matters most, burn-in and system-level test for accelerators, is smaller but growing faster still [10]. That is the demand pull under everything that follows.
Why Southeast Asia, why now
The pull is policy as much as economics. US export controls tightened through 2023 and 2024, and the volatility that followed through 2025 and 2026 kept pushing customers to qualify test sites outside China [14]. The leverage in that is arithmetic. Greater China ran about 75% of global OSAT in 2023, so the pool of back-end work that policy could dislodge is enormous, while Malaysia handles an estimated 13% of global chip assembly and test, the largest established cluster outside China and Taiwan [9]. When the big pool is what moves and the smaller base is where it lands, even a modest share shifting south is an outsized gain for Southeast Asia. That asymmetry, not the region's size today, is why the timing matters.
Why not just keep test next to the fab? Because it does not have to be there. A finished wafer is small and hugely valuable per gram, so shipping it to a cheaper site costs little, whereas test and burn-in are labour-, power- and capacity-hungry and lower-margin, work that gravitates away from high-cost, resource-constrained Taiwan. The packaging that must stay coupled to the fab does stay put, the CoWoS interposer and the HBM stacking remain captive at the foundries and memory makers. Korea’s memory giants make the point in concrete: rather than outsource, SK hynix and Samsung are pouring billions into captive HBM packaging-and-test at home, SK hynix’s roughly US$13 billion Cheongju plant and Samsung’s Cheonan and Onyang lines [35]. What travels is the separable test and mid-tier packaging, and it travels to wherever is cheapest and most neutral.
The migration is not abstract. KYEC, Taiwan’s largest independent tester, divested its entire China testing operation during 2025 even as it built a new plant in Singapore [12]. Test-equipment maker Teradyne pulled roughly US$1 billion of production out of Suzhou under the same pressure [13]. Trio-Tech shows the other side of the same move: its China revenue fell about 84% over the nine months to March 2026 while group revenue rose 85%, consistent with AI final-test work leaving China for its Singapore and Malaysia labs [39]. The rules themselves keep shifting, though. A January 2025 rule that would have swept Malaysia into a tiered AI-chip export regime was rescinded that May, and Washington has drafted and pulled back further AI-chip export measures since, most recently a broad rule withdrawn in March 2026 [14]. No single rule has stuck. The signal is the pattern, not the particulars: the regulatory line can be redrawn at short notice, and that uncertainty pushes customers to spread their back-end work across several countries rather than bet on one, which is exactly what favours the region.
Southeast Asia is where that capacity is landing. The table below is the map at a glance.
The countries are not competing on the same terms; each pulls a different policy lever at a different point on the chain. Malaysia leans on the deepest existing ecosystem and its National Semiconductor Strategy, which had drawn RM85 billion of approved investment by the end of 2025 against a 60,000-worker target, and is nudging local firms up-market through programmes like SemiconStart [36]. Singapore competes on value and neutrality rather than cost, winning the equipment and high-end test slice, AEM’s tooling and KYEC’s neutral Singapore plant [4][21]. Vietnam is the aggressive challenger, with a national target of ten advanced test-and-packaging plants by 2030 and incentives that have pulled in Samsung, Intel and Amkor [28][31]. Thailand’s Board of Investment has drafted a national roadmap targeting more than 2.5 trillion baht of investment and a “chip made in Thailand” by 2050, skewed toward power electronics and automotive [37]. The Philippines offers CREATE-era incentives over a large but mostly foreign-owned assembly-and-test base [31], and Indonesia is earliest-stage, a government test house and a joint-venture push from a low, import-dependent base [28][31]. For an equity investor the map compresses further: Malaysia is where the listed cluster actually sits (KESM, Inari, Unisem, MPI), Singapore adds AEM and KYEC’s site extension, and Vietnam, the Philippines and Indonesia matter strategically but offer little directly listed exposure because their new capacity is largely foreign or captive.
Penang is the anchor, and it straddles the island and the mainland. On the island, at Bayan Lepas, sit KESM’s independent burn-in lines, and Cohu, a US test-equipment and handler company adjacent to Singapore’s AEM, opened a test-design centre there in June 2024, deepening the local engineering base [16]. Across the water on the mainland, in Seberang Perai and specifically Batu Kawan, the heavy new capacity is going up: SPIL’s roughly RM6 billion (about US$1.27 billion) packaging-and-test plant at Bandar Cassia, the captive TF-AMD joint venture that runs AMD’s Penang assembly and test, Inari’s P34 line serving a new US memory customer, Micron’s assembly-and-test operations, and now Chipbond’s new plant, with Intel investing on the order of US$7 billion in captive advanced packaging in Penang alongside them [9][17][18][22]. Smaller but riding the same thesis, Trio-Tech runs a new leased final-test facility in Perai, where the single AI customer behind its recent revenue surge is served [39]. The split matters: the island holds the legacy base, while the mainland at Batu Kawan is where most of the new capacity is rising, a strait apart rather than one campus. Not all of it is AI, ASE's newer Bayan Lepas plant, P5, is wire-bond for automotive and edge, not accelerators [19], and the AI share is selective. But taken together, it is one of the densest back-end clusters outside Taiwan.
Two business models
The capacity race is really a contest between two models.
The turnkey OSAT channel bundles packaging and test on one floor and captures the test work once its own line is online. SPIL, an ASE subsidiary, is the local example: it broke ground at Batu Kawan in May 2024 on a plant meant to offer turnkey packaging-and-test under one roof [17].
The independent-test channel is the standalone tester extending qualified capacity into a new geography. KYEC is the textbook case: test is roughly 95% of its revenue, and it opened a S$100 million plant in Singapore in 2026 [12][21]. It is no longer alone; Chipbond, a Taiwanese driver-IC bumping-and-test specialist, opened a plant of close to US$200 million at Batu Kawan in early 2026 [22].
The two do not move at the same speed, and the reason is qualification. Putting a new test supplier into a customer’s flow is a months-long proof of yield and reliability, framed by KESM’s own management as a six-to-twenty-four-month exercise [23]. An independent tester opening a site for customers it already qualifies elsewhere runs a site extension, not a cold qualification, so it moves first. A turnkey OSAT only wins the test work once its own floor is built and proven. That head start is, in practice, the whole game.
The players, by role
One filter runs through every name below: how close is the AI link, really? It helps to keep three tiers apart. Direct AI test is burn-in, final test and system-level test for accelerators and HPC chips. AI-infrastructure adjacent is the optical transceivers, power, analog, sockets and inspection that surround those chips without testing them. General back-end is the automotive, RF, industrial, consumer and EMS work that dominates most of these companies’ revenue today. Very few of these names are in the first tier; the market too often prices them as if they were.
Independent testers (the purest bet on the theme). KESM Industries (Bursa: 9334) is the regional anchor, a listed independent burn-in and reliability-test house that describes itself as the world’s largest independent provider in that niche, defining independent as not related to any of its customers, with an automotive base, lines at Bayan Lepas on Penang island and a Malaysian footprint extending to Petaling Jaya, and for the first time it named “artificial intelligence related chips” as a demand driver in its 2026 filings while tripling capex [15]. KYEC (TWSE: 2449) is the Taiwanese pure-play now Singapore-relevant, serving 48% of the world’s fifty largest chipmakers with NVIDIA among named customers and building its own high-power burn-in ovens [12]. Trio-Tech International (NYSE American: TRT) is a small US-listed final-test and burn-in house with regional operations, and the clearest China-plus-one case in the group: its recent revenue surge is one customer's AI final-test work relocated out of China [39]. Chipbond (TWSE: 6147) is the newest entrant, the second Taiwanese tester to plant capacity in Penang [22].
Turnkey OSATs (packaging plus test). ASE Technology Holding (NYSE: ASX; TWSE: 3711), parent of SPIL, is the mega-cap shown for scale; its 2025 revenue of about NT$645 billion splits roughly 59% semiconductor packaging-and-test and 40% electronic manufacturing services, a reminder that even the group flagbearer is only part test [24]. Among listed Malaysian OSATs, Inari Amertron (Bursa: 0166) is the largest but is really an RF and optoelectronics specialist: radio-frequency work was about 61% of revenue in its most recent quarter, optoelectronics about a third. Inari does not disclose its largest customer’s share, but roughly 87% of FY2025 revenue was booked in Singapore, a widely used proxy for its heavy reliance on one principal customer, generally identified by analysts as Broadcom. Its AI angle is real but specific, 800-gigabit optical transceivers for data-centre interconnect rather than accelerator test [20]. Unisem (Bursa: 5005) is a broad assembly-and-test house leaning on a single large US analog customer that brokers identify as Monolithic Power Systems (its 2024 annual report discloses one customer above 10% of revenue), and it is raising up to RM742 million through a placement to expand [25][26]. Malaysian Pacific Industries (Bursa: 3867), through Carsem, is automotive-heavy and bought Infineon’s Bangkok/Nonthaburi back-end plant in 2026 with a long-term supply agreement attached, the second Infineon back-end site to pass to a Southeast Asian OSAT after ASE’s 2024 Cavite deal, which gives its Thai expansion built-in offtake [9][27][28].
Equipment and adjacent names. AEM Holdings (SGX: AWX) is the most direct equipment play, but it sits a layer below the testers: it builds the handlers, system-level-test cells and burn-in equipment that work with the tester. It has been Intel’s principal test-handling supplier for over a decade, with more than 35,000 system-level-test sites deployed, and its active thermal control, which keeps high-power AI die cool during test, sits directly in the accelerator’s path; a 2025 Intel Foundry partnership and a high-volume ramp for an AI/HPC customer lifted FY2025 revenue 5% to S$399 million, driven by its Test Cell Solutions segment. The flip side is concentration: one customer was about 38% of group revenue in 2025 [4]. ViTrox (Bursa: 0097) and Pentamaster (Bursa: 7160) are inspection and automated-test equipment makers; JF Technology (Bursa: 0146) makes the sockets and contactors [5]; Globetronics (Bursa: 7022) is a sensor-led OSAT now shrinking [29]. In Thailand, Hana Microelectronics (SET: HANA) is a hybrid EMS-and-OSAT: about 63% of 2025 sales was board-level PCBA (printed-circuit-board assembly) and 31% IC assembly-and-test, at an 8% gross margin. Tellingly, it cut capital spending sharply in 2025 as IC demand softened, a useful reminder that not every regional back-end name is riding the AI wave [30]. None of these is an independent test house, and treating them as one is the easiest mistake in this sector.
Put the roster against the numbers and the theme separates cleanly: the AI-exposed testers are growing, and the consumer- and RF-cyclical names are not.
So where does that leave the roster? Before valuation enters the picture, the names sort into three buckets by exposure:
The theme, in other words, is not “buy Southeast Asian back-end.” It is to find where the pricing and the durability disagree. That is what the rest of this piece is for.
The free map tells you who is exposed. The paid question is what the market is already paying for, where that looks wrong, and which exposures are durable enough to deserve the multiple. Below, for paying subscribers, we compare the names on valuation and EBITDA margin, weigh customer concentration and the hidden margin question of who owns the tools, and set out what we are watching into the 2027 capacity wall.